module LEDInterface
(
input clk,
input rst_n,
input CS,
input wr_n,
input [7:0] addr,
input [31:0] data_wr,
output reg [3:0] LED
);

always@(posedge clk,negedge rst_n) begin 
if(!rst_n) begin 
	LED<=0;
end 
else if((!wr_n)&&(CS))begin 
	LED<=data_wr[3:0];
end 
else
	LED<=LED; 
end 


endmodule 